The present invention relates to computer memory architectures and in particular to a shared row buffer system for asymmetric memories.
Electronic circuits for providing electronic memory are a principal component of modern computer architectures and provide storage of the instructions of computer programs and the data used by the programs at memory addresses.
There is a trade-off between the capacity or density of electronic memory circuits (how much can be stored) and how quickly the data can be accessed (latency). Typical memory systems may employ a variety of different memory architectures, for example, including multiple levels of cache memory, primary dynamic random access memory and secondary magnetic storage memory. These architectures present a hierarchy of different memory technologies with different capacities and latencies and may be arranged to allow data that is frequently accessed to be available in the low capacity, low latency structures as copied from the high-capacity, high latency structures. The data copied in the low capacity, low latency is constantly changed (through cache management techniques and page swapping) in an attempt to keep copies of the most frequently accessed data in that low latency structure.
It is also known to produce asymmetric memories having some high-capacity, high latency banks (slow) and some low capacity, low latency banks (fast) within a single memory device and typically using a single memory technology. Asymmetric memory has a superficial resemblance to the hierarchical memory structures discussed above, but differs in that normally the data is not held redundantly in the asymmetric memory in order to maximize capacity. Rather, unique data is allocated between the fast and slow portions of the asymmetric memory so that any given data element is held in only one of the fast and slow memory banks at a location ideally comporting with its access frequency.
There is typically a considerable cost in terms of time and processor resources in moving data between portions of the asymmetric memory. Such movement normally entails reading an entire page of data to the processor through a memory channel and then writing it back to the new location. During this time the memory channel is incapacitated and substantial processor resources are used. This cost of moving data makes it difficult to ensure frequently accessed data is in the fast memory banks. This is because changing workload patterns frequently change the identity of the data pages that are most frequently accessed.